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Global Standards for the Microelectronics IndustryLPDDR5 overview and operationOsamu NagashimaMicron, MBULPDDR5 WorkshopCopyright 2019 Micron
Agenda Architecture Outline LPDDR4 vs. LPDDR5 Comparison Bank Operations Pin Configuration Refresh Operation Latency variations Dynamic Voltage Frequency Scaling : DVFS Byte mode MR control Decision Feedback Equalization : DFELPDDR5 Workshop
Agenda Architecture Outline LPDDR4 vs. LPDDR5 Comparison Bank Operations Pin Configuration Refresh Operation Latency variations Dynamic Voltage Frequency Scaling : DVFS Byte mode MR control Decision Feedback Equalization : DFELPDDR5 Workshop
Architecture Outline Simplify Die Architecture Only Single Channel configuration No dual channel definition Rotated ball out concept for dual / quad channel PKG X16 and X8 are defined as native configuration Addressing are defined from 2Gb/die to 32Gb/die Lower power consumption Lower VDD2 and VDDQ supply than LPDDR4 Dynamic Supply Voltage ControlLPDDR5 Workshop
Architecture Support various requirements Flexible Architecture Programable Bank organization Byte mode and x16 mode High reliability function High data rate friendly clocking system Dual Clock for CA bus and DQ bus Low Power features Reduce data transfer Clocking power optimizeLPDDR5 Workshop
Architecture Flexible training schemes QD training : FIFO, pre-programed CA training : Consolidated CBT Foreground / background ZQ calibration Support equivalent formfactor as LPDDR4 POP MCP FBGALPDDR5 Workshop
Agenda Architecture Outline LPDDR4 vs. LPDDR5 Comparison Bank Operations Pin Configuration Refresh Operation Latency variations Dynamic Voltage Frequency Scaling : DVFS Byte mode MR control Decision Feedback Equalization : DFELPDDR5 Workshop
LPDDR4 vs. LPDDR5 mentsSupplyVDD2H1.05VVDD2L0.9V (1.05V)Can support mono VDD2(1.05V)0.5V term / 0.3V un-termDVFSQ supportVDDQ0.6VLPDDR5 Workshop
LPDDR4 vs. LPDDR5 ComparisonItemLPDDR4XLPDDR5Channel configuration2ch / 1ch1chBank organization8Banks4Bank Group 4Banks / 8Banks /16BanksPage Size2Kbyte (x16)1Kbyte (x8)BG: 2Kbyte (x16), 1Kbyte (x8)8Bank: 4Kbyte (x16), 2Kbyte (x8)Maximum Data rate4266Mbps6400MbpsDQs per Chx16 / x8x16 / x8Burst length16 / 3216, 32 interleave and 32 seamlessCommentsArchitectureLPDDR5 WorkshopMR selectable8Banks and 16Bankssupport 32 seamless
LPDDR4 vs. LPDDR5 ComparisonItemLPDDR4XLPDDR5CommentsClock inputCKCK / WCKseparate clock for CA and DQSynchronizationN/AWCK2CK sync is requiredFrequencyCK up to2.1GHzCK up to 800MHzWCK up to 3.2GHzClock terminationVSS ODTVSS ODTWCK CK ratioN/A4:1 and 2:1 supported2:1 can support up to 3.2GbpsDuty Cycle AdjustmentN/Aprogrammable DCAMR controlDuty Cycle MonitorN/ARead/Write one monitorClockingLPDDR5 Workshop
LPDDR4 vs. LPDDR5 ComparisonItemLPDDR4XLPDDR5CommentsPin count6pins CA[5:0]7pins CA[6:0]Removing CKECA rateSDRDDRSame Max CA bandwidthLink protectionN/AOptional : Link ECCOptional : SECDED is supportedRead strobeDQSRDQSsingle ended ( t or c) supportedWrite strobeDQSWCKsingle ended ( t or c) supportedpins per byte11 pins8DQ 1DMI 2DQS13 pins8DQ 1DMI 2RDQS 2WCKCA BusData busLPDDR5 Workshop
LPDDR4 vs. LPDDR5 ComparisonItemLPDDR4XLPDDR5CommentsDQ / CA schemeLVSTL 0.6LVSTL 0.5/0.3DVFSQ, 0.3V for un-terminatedMask shapeRectangularHexagonalZQ CalibrationCommandBack ground and commandReset VIHVDD20.8*VDD2HCS input levelLVSTL 0.6Sync mode fixed Vref,Smaller swing CMOSDFEN/A1 TAP DFEInterfaceLPDDR5 WorkshopZQ connected to VDDQSync mode VrefCS VDD2H/3
LPDDR4 vs. LPDDR5 ComparisonItemLPDDR4XLPDDR5CommentsClock power reductionSingle ended CK and DQSSingle Ended CK andWCKSingle ended support with tor c selectableDynamic VoltageFrequency ScalingN/ACore and DQ scalingData copyN/AVertical copyWrite XN/AsupportedPASRBank and Segment MaskSegment MaskPAARN/ASegment MaskLow PowerLPDDR5 WorkshopAuto Refresh Segment Mask
LPDDR4 vs. LPDDR5 ComparisonItemLPDDR4XLPDDR5CommentsCommand Bus Trainingx16 and x8differentUnified training scheme,Rise and Fall CK edgeseparatedTwo options w/ and w/o VreftrainingRead DQ trainingsupportedsupportedFiFO Read/WritesupportedsupportedRDQS TrainingDQS trainingmodeEnhanced RDQS training /RDQS toggle modeTrainingLPDDR5 Workshop8 depth
LPDDR4 vs. LPDDR5 ComparisonItemLPDDR4XLPDDR5CommentsFrequency Set Point2sets3setsBL command selectBL16 and BL32by CA opBL16 and BL32 by differentcommandcan support in BG mode and16bankTiming monitortDQS2DQ OSCtWCK2DQI OSC andtWCK2DQO OSCCannot support simultaneouscountTemp OffsetsupportedsupportedVref programCA and DQCA, per Byte DQOther functionsLPDDR5 WorkshopSingle ended CK/WCK Vref VDDQ/2 fixed
LPDDR4 vs. LPDDR5 ComparisonItemLPDDR4XLPDDR5CommentsMRW byte selectableN/ASupportedMR control Byte selectableMRW for Byte modeVRCGsupportedsupportedNon Target ODTdeletedSupportedNo command bus snoopPost PKG RepairsupportedsupportedGuard Key protectionSerial ID MRN/A8MRs for serial IDOther functionsLPDDR5 Workshop
Agenda Architecture Outline LPDDR4 vs. LPDDR5 Comparison Bank Operations Pin Configuration Refresh Operation Latency variations Dynamic Voltage Frequency Scaling : DVFS Byte mode MR control Decision Feedback Equalization : DFELPDDR5 Workshop
Bank Operations LPDDR5 support three Bank organization. There are different burst mode for each bank organization. Selected by mode register write Please refer to read/write operation. 8B mode Full Frequency range BG mode 4Bank group with 4Banks per Bank group. High data rate support (more than 1.6GHz WCK) 16B mode Low data rate support (equal and less than 1.6Ghz WCK)LPDDR5 Workshop
Bank OperationsBG 31288 DQ DMI128128BG 22568 DQ DMIBG 1Bank0-3Bank4-7Bank0-3Bank4-7CA BusDQ Byte 1256BG 0DQ Byte 0128128Bank 3Bank 2Bank 18 DQ DMIBG 28 DQ DMIDQ Byte 0BG 1LPDDR5 Workshop8Banks Mode ConfigurationBG 0BG 3CA BusDQ Byte 1128Bank 04Banks / 4Bank Groups ConfigurationBank0-3Bank4-7Bank0-3Bank4-7
Bank Operations12816Banks Mode ConfigurationBank4-7DQ Byte 1Bank8-11Bank12-15128CA BusDQ Byte 0Bank0-3Bank0-3Bank4-7Bank8-11Bank12-15LPDDR5 G0BA2BA2BG1B4BA3NOTE 1 BA0-3: Bank Address, BG0-1: Bank Group address,B4: Burst Starting Address.
Agenda Architecture Outline LPDDR4 vs. LPDDR5 Comparison Bank Operations Pin Configuration Refresh Operation Latency variations Dynamic Voltage Frequency Scaling : DVFS Byte mode MR control Decision Feedback Equalization : DFELPDDR5 Workshop
Pin Configuration Minimizing pin count increase CA Bus 7 CA input, increase 1pin from LPDDR4 Removing CKE, decrease 1pin from LPDDR4 DQ Bus 2 differential WCK, increase 1pin from LPDDR4 Combined differential RDQS/DMI/ParityLPDDR5 Workshop
Pin ConfigurationPins Per-Byte Signal List/Description for Link Protection disabledPinName#11 DMI#12RDQS t#13RDQS cDBIEnableNoYesNoYesNoYesSE RDQS(MR20 OP[1:0] 01WriteReadDMN/ADMIDBIN/ARDQS tN/ARDQS tN/AN/AN/AN/ASE RDQSLink Protection disabled(MR20 OP[1:0] 11WriteReadDMN/ADMIDBIN/AN/AN/AN/AN/ARDQS cN/ARDQS cDiff RDQS(MR20 OP[1:0] 10WriteReadDMN/ADMIDBIN/ARDQS tN/ARDQS tN/ARDQS cN/ARDQS cPins Per-Byte Signal List/Description for Link Protection enabledPinName#11 DMI#12RDQS t#13RDQS cLPDDR5 WorkshopDBIEnableNoYesNoYesNoYesSE RDQS(MR20 OP[1:0] 01WriteReadDMparityDMIparityparityRDQS tparityRDQS tN/AN/AN/AN/ASE RDQSLink Protection enabled(MR20 OP[1:0] DQS cN/ARDQS cDiff RDQS(MR20 OP[1:0] 10WriteReadDMparityDMIparityparityRDQS tparityRDQS tN/ARDQS cN/ARDQS c
Pin ConfigurationSymbolCK t, CK cCSCA[6:0]DQ[15:0]WCK[1:0] t, WCK[1:0] cRDQS [1:0] t , RDQS[1:0] cDMI[1:0]ZQVDDQ, VDD1,VDD2H, VDD2LVSSRESET nLPDDR5 WorkshopTypeInputInputInputI/OInputRDQS t :I/O, RDQS c :OutputI/OReferenceSupplyGNDInput
Agenda Architecture Outline LPDDR4 vs. LPDDR5 Comparison Bank Operations Pin Configuration Refresh Operation Latency variations Dynamic Voltage Frequency Scaling : DVFS Byte mode MR control Decision Feedback Equalization : DFELPDDR5 Workshop
Refresh Operation LPDDR5 refresh operation is any time 8B mode base regardless bankarchitecture. LPDDR5 support all bank refresh and per bank refresh 8B / 16B mode : per bank refresh use BA[2:0] as bank address BG mode : per bank refresh use BG0, BA[1:0] as bank address 8times of per bank refresh are treated as one all bank refresh All 8B must be refreshed within 8times of per bank refresh operations. Refresh interval definition Actual Refresh interval : tREFIe at given condition is defined with tREFI andrefresh multiplier (MR4 OP[4:0]) tREFIe tREFI * refresh multiplierLPDDR5 Workshop
Refresh Operation Refresh can be pull-in or postponed. # of pull-n and postpone defiedwith RM.ExampleLPDDR5 Workshop
Refresh 01B01110B01111B11111BRefresh rateLow temp. Limit8 x tREFI6 x tREFI4 x tREFI3.3 x tREFI2.5 x tREFI2.0 x tREFI1.7 x tREFI1.3 x tREFI1 x tREFI0.7 x tREFI0.5 x tREFI0.25 x tREFi, no de-rating0.25 x tREFi, with de-rating0.125 x tREFi, no de-rating0.125 x tREFi, with de-ratingSDRAM High temperature operating limitexceededLPDDR5 WorkshopMax. No. of pulledin or postponedREFabMax. Intervalbetweentwo REFabMax. No. of REFabwithin max(2xtREFIx refresh ratemultiplier,16xtRFC)Per-bank RefreshN/A112234568888888N/A2 x 8 x tREFI2 x 6 x tREFI3 x 4 x tREFI3 x 3.3 x tREFI4 x 2.5 x tREFI5 x 2.0 x tREFI6 x 1.7 x tREFI7 x 1.3 x tREFI9 x 1 x tREFI9 x 0.7 x tREFi9 x 0.5 x tREFI9 x 0.25 x tREFI9 x 0.25 x tREFI9 x 0.125 x tREFI9 x 0.125 x tREFIN/A224468101216161616161616N/A1/8 of REFab1/8 of REFab1/8 of REFab1/8 of REFab1/8 of REFab1/8 of REFab1/8 of REFab1/8 of REFab1/8 of REFab1/8 of REFab1/8 of REFab1/8 of REFab1/8 of REFab1/8 of REFab1/8 of REFabN/AN/AN/AN/A
Refresh Operation LPDDR5 support Partial Array Refresh Control (PARC) to reduce IDD5power. When MR25 OP[6] : PARC is set to 1B, LPDDR5 skip refresh operation basedon Segment Mask: MR23 OP[7:0] information.LPDDR5 Workshop
Agenda Architecture Outline LPDDR4 vs. LPDDR5 Comparison Bank Operations Pin Configuration Refresh Operation Latency variations Dynamic Voltage Frequency Scaling : DVFS Byte mode MR control Decision Feedback Equalization : DFELPDDR5 Workshop
Latency variations Read Latency Read latency has dependency with following functions. Byte modeRead DBI or Read Data Copy (one of each)Read Link ECCDVFSC Read latency has defined with three tables Link ECC off / DVFSC disabled Link ECC off / DVFSC enabled Link ECC on / DVFSC enabledLPDDR5 Workshop
Latency variations Read latency set definition Read latency defined with set 0, set 1 and set 2RL Set 0 applies when no features are enabled.RL Set 1 applies when one feature is enabled (1 or 2).RL Set 2 applies when two features are enabled.Feature12LPDDR5 WorkshopDescriptionByte ModeRead DBI and/or Read Data Copy
Latency variationsRead Latencies for Link ECC off case (DVFSC disabled)Data RateLower 750320037334267480055006000Data RateUpper 7503200373342674800550060006400WCK:CK Ratio2:14:1LPDDR5 WorkshopLower ClockFrequency Limit ( 688750Upper ClockFrequency Limit ( 688750800Read LatencySet 0Set 1Set 022000011223444
Latency variationsRead Latencies for Link ECC off case (DVFSC enabled)Data RateLower Limit(Mbps)Data RateUpper 0Data RateLower Limit(Mbps)320037334267480055006000Data RateUpper Limit(Mbps)373342674800550060006400WCK:CK Ratio2:14:1Read LatencyLower ClockFrequency Limit ( )(MHz)Upper ClockFrequency Limit ( )(MHz)Set 0Set 1Set 101235661014357000000Read Latencies for Link ECC on case (DVFSC disabled)WCK:CK Ratio4:1LPDDR5 WorkshopLower ClockFrequency Limit ( )(MHz)400467533600688750Upper ClockFrequency Limit ( )(MHz)467533600688750800Read LatencySet 0121315171819Set 1(Byte Mode)131416182021nRBTP[nCK]223444
Latency variation Write Latency has impact by DVFSC Users can select set A or set B via MR3 OP[5] same as LPDDR4.Write Latency: DVFSC EnabledMR1OP[7:4]WCK:CK DR5 WorkshopData Rate Range[Mbps]Lower Limit Upper Limit( )( )4053353310671067160040533533106710671600CK Frequency Range[MHz]Lower Limit Upper Limit( )( )1013313326726740056767133133200WLSet ASet B446223468234UnitnCKnCKnCKnCKnCKnCK
Latency variationWrite Latency: DVFSC DisabledMR1 OP[7:4]WCK:CK 14:14:14:14:14:14:14:14:14:14:1LPDDR5 WorkshopData Rate Range[Mbps]CK Frequency Range [MHz]WLLower Limit( )Upper Limit( )Lower Limit( )Upper Limit( )Set ASet KnCKnCKnCKnCKnCKnCKnCKnCKnCKnCKnCKnCKnCKnCK
Agenda Architecture Outline LPDDR4 vs. LPDDR5 Comparison Bank Operations Pin Configuration Refresh Operation Latency variations Dynamic Voltage Frequency Scaling : DVFS Byte mode MR control Decision Feedback Equalization : DFELPDDR5 Workshop
Dynamic Voltage Frequency Scaling : DVFS LPDDR5 support two kind of DVFS scheme to reduce power. To enableDVFS function, there are frequency upper limits. DRAM internal power reduction : DVFSC Interface power reduction : DVFSQLPDDR5 Workshop
Dynamic Voltage Frequency Scaling : DVFS DVFSC stands for DVFS core Concept Power supply : two different stable power supplies are required. VDD2H : 1.05V nominal VDD2L : 0.9V nominal LPDDR5 internally change supply source based on MR OP condition MR19 OP[1:0] controls DVFSC enable / disable. DVFSC can support up to WCK 800MHzLPDDR5 Workshop
Dynamic Voltage Frequency Scaling : DVFS DVFSC timing 5te0te1te2te3CK cCK ttFCCACommandWCK tCAS CAS WRCASWRWriteDesDesDesDesMRW MRW MRW MRW1122DesDesDesDesFSP Switch,VRCG OnDesDesDesDesDesDestWCK2CKWCK ctWCK2DQItWPSTDQ[15:0]VDD2HVDD2LDRAM internal periphery circuit voltageLPDDR5 WorkshoptVRCG DISABLEDesMRW MRW MRW MRW1122DesDesDesVRCG OffDesDesValidValidACT-1ValidValidACT-2DesDes
Dynamic Voltage Frequency Scaling : DVFS DVFSC conceptual block diagramVDD2HEnabled when DVFSC isdisabledVDD2LEnabled when DVFSC isenabledDRAM Peripheral Circuit BlockLPDDR5 Workshop
Dynamic Voltage Frequency Scaling : DVFS DVFSQ stands for DVFS VDDQ Concept Power supply : two different power supply level is supported. DVFSQ disabled : VDDQ 0.5V nominal, Can support terminated and un-terminated I/F DVFQS enabled : VDDQ 0.3V nominal, Only support un-terminated I/F During VDQQ ramp up and down, LPDDR5 can operate with DVFSQ enabled condition. MR19 OP[3:2] controls DVFSQ enable / disable.LPDDR5 Workshop
Dynamic Voltage Frequency Scaling : DVFS DVFSQ timing exampleCK te4tf0tf1tg0tg1tg2CK tCACAS CASWRWRDesDesDesDesDesDesDesDesDesMRW- MRW- MRW- DesDes MRW1122MRW- MRW- MRW- DesDes MRW1122MRW- MRW- MRW- DesDes sFSP Switch withVRCG EnableDestFCMRW MR16 OP[6] 0DesMRW28 OP[1] 1ZQ StopDesDesDesACT-1ACT-2DesDesCAStZQStopWCK tWCK ctWCK2DQItWCKPSTDQ[15:0]VDDQ 0.5VVDDQ 0.3VVDDQ 0.3VLPDDR5 Workshop
Agenda Architecture Outline LPDDR4 vs. LPDDR5 Comparison Bank Operations Pin Configuration Refresh Operation Latency variations Dynamic Voltage Frequency Scaling : DVFS Byte mode MR control Decision Feedback Equalization : DFELPDDR5 Workshop
Byte mode MR control Byte mode devices share CS and CA. Some Mode Registers are need to be programed differently for upperbyte and lower byte device MR20 OP[5:4] controls MR write for upper byte and lower bytedevice MR13 OP[1:0] Thermal OffsetMR25 OP[5:4] CA BUS TERM, CK BUS TERMMR41 OP[4] PPREMR41 OP[7:5] NT DO ODTLPDDR5 Workshop
Byte mode MR control Vref code has different control scheme to selectable Vref set forupper byte device and lower byte device Vref CA : MR12 OP[7] VBS (VREF(CA) Byte Select) Vref DQ : upper byte and lower byte use separate MR14 and MR15 Duty Cycle Adjustment has separate OP for upper and lower byte.LPDDR5 Workshop
Agenda Architecture Outline LPDDR4 vs. LPDDR5 Comparison Bank Operations Pin Configuration Refresh Operation Latency variations Dynamic Voltage Frequency Scaling : DVFS Byte mode MR control Decision Feedback Equalization : DFELPDDR5 Workshop
Decision Feedback Equalization : DFE LPDDR5 provide Decision Feedback Equalization (DFE) capability asoptional feature. Byte controllable function MR24 OP[2:0] lower byte, MR24 OP[6:4] upper byte DFE support higher than 800MHz WCK.LPDDR5 Workshop
End of PresentationLPDDR5 Workshop
CA training : Consolidated CBT Foreground / background ZQ calibration Support equivalent formfactor as LPDDR4 POP MCP FBGA. LPDDR5 Workshop. Agenda . WCK2CK sync is required. Frequency. CK up to 2.1GHz. CK up to 800MHz WCK up to 3.2GHz
