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Elma VPX BackplanesTechnical Reference GuideSYSTEMS SOLUTIONSENCLOSURES & COMPONENTSROTARY SWITCHESCABINETSwww.elma.com

ELMA.COMABOUTARCHITECTUREThe VPX reference guide provides relevant reference material for Elma's VPX backplanes. The information provided may change at anytime. OpenVPX is a process that defines system level VPX interoperability for multi-vendor, multi-module, integrated systems environments.The OpenVPX process defines clear interoperability points necessary for integration from module to module, module to backplane andbackplane to chassis.OpenVPX purpose: Control and manage the assignment of VPX pins to functional planes in an interoperable architecture To get a high-degree of interoperability, while leaving room for sensor- /application-specific augmentation To make the process of developing VPX-based solutions from the lab to the field much more efficient in cost, time, quality, and repeatabilityOpenVPX provides a descriptive language for identifying slot and module requirements and backplanes capability. It also provided withthe part number configuration more information on the control and fabric planes, including the signal speeds.VPX STANDARDSThe VITA trade association provides members with the ability to develop and to promote open technology standards. The VITA StandardsOrganization (VSO) is an ANSI-accredited group that provides members with a means to work together to define and develop key computerspecifications such as the family of VPX standards, which include VITA 46.x, VITA 48.x, and VITA 65. Elma is a key contributor to the Working Groups related to VPX.246.0VPX66.1Optical Full size Dual MT variant46.1Parallel VME on VPX66.2Optical ARINC 801 Termi variant46.3RapidIO on VPX66.3Optical Mini Expanded Beam46.4PCI Express on VPX66.4Optical Half size MT variant46.6Gigabit Ethernet Control Plane on VPX67.0RF and Mixed Signal overview46.710 G Ethernet on VPX67.13U RF46.8VDSTU InfiniBand on VPX67.26U RF46.9Rear IO on VPX67.3Flexible multi-level RF on VPX46.10VPX RTM68.0VDSTU VPX SI46.11System Management on VPX68.1VDSTU VPX SI backplane48.0 – 48.8VPX REDI: Mechanical Cooling68.2VPX SI Mezzanine (under development)57.1 – 57.2FMC: FPGA Mezzanine Cards Base60Viper connector65.0OpenVPX61Alternate XMC connector65.1New Slot and Module Profiles62VPX power supplies66.0Optical Overview63Hypertronics connectorVPX BACKPLANES

ELMA.COMPROFILESCHANNELS: FAT, THIN, ULTRA THINRx1 Rx1-Tx1 Tx1Rx2 Rx2-Rx3 Rx3-Tx1 Tx1Tx2 Tx2-Tx3 Tx3Rx4 Rx4-Rx1 Rx1Tx2 Tx2-Tx3 Tx3Tx4 Tx4-Rx2 Rx2Rx3 Rx3-Tx4 Tx4-Rx4 Rx4-Fat Pipe: A channel that is comprised of four links (4 Tx pairs 4 Rx pairs) is now being referred to as a Flat Pipe or byuse of the x4 nomenclature. 10Gbps capable 10GBase-KX4, 10GBase-BX4, 10GBase-T, PCIe-x4, sRIO-x4, Infiniband-x4Rx1 Rx1-Tx1 Tx1Rx2 Rx2-Tx1 Tx1-Rx1 Rx1-Tx2 Tx2Tx2 Tx2-Rx2 Rx2-Thin Pipe: A channel that is comprised of two links (2 Tx pairs 2 Rx pairs) is now being referred to as a Thin Pipe or by useof the x2 nomenclature. 5Gbps capable 10/100/1000Base-T, 1000Base-BX, PCIe-x2, sRIO-x2, Infiniband-x2Rx1 Rx1-Tx1 Tx1Tx1 Tx1-Rx1 Rx1-Ultra-thin Pipe: A channel that is comprised of one link (1 Tx pair 1 Rx pair) is now being referred to as an Ultra Thin Pipeor by use of the x1 nomenclature. 10GBase-KR, IGBase-KX, PCIe-x1, sRIO-x1, Infiniband-x1aVPX BACKPLANES3

ELMA.COMPROFILESSLOT PROFILESVITA 65 defines OpenVPX in terms of four types of Profiles: Slot Profiles,Backplane Profiles, Module Profiles and Chassis Profiles. Slot Profiles havea type, board size and clock variation. Slots have rows that are definedto support a variety of Pipe sizes or module apertures. Slot Profiles definewhere pipes or apertures are located and also indicated user defined waferlocations.Backplane Profiles define how the Slots are interconnected. Backplane Profiles also define the bandwidth capability of the Pipes. Module Profilesindicate which Pipes or Apertures are supported and the signaling protocoland data rate associated with each Pipe. A Module Profile are fully compatible with a single Slot Profile but can be used in Slots that do not fullysupport all the defined channels.The system integrator must ensure that pipes that are connected togetherin a backplane have modules that support the same signaling protocols.The chart below indicates how the various features of a Slot Profile aredescribed.SLTU y – PAY - nXnXnX-1X.x.x-nBoard SizeU 3 or 6y Clock variations p parallel termination s series termination x radial - not defined Omitted field bussedSlot type PAY payload STO storage PER peripheral SWH switch TIM timingn # pipesor connectorpatternsVITA 65Sections10 or 14X Type of Pipes or AperturePipes (number of diff.pairs or discrete fibers S Single Pipe (1) U Ultra-thin (2) T Thin (4) F Fat (8) M Ten (10) W Twelve (12) D Double (16) Q Quad (32) O Octal (64)Connector aperture name(Connector Module size) A 66.1 (full) B 66.2 (full) C 66.3 (full) E 66.4/ 67.1/ 67.3A (half) G 67.2/ 67.3B (full) H 67.3C (full new) J 67.3D (half new) K 67.3E (full half new)Note: That order of Pipes is from top to bottom in the physical slot4VPX BACKPLANESn a line in the SlotProfile spreadsheetidentifying specificconnector aperturepattern (if any) andRF or optical modulepopulation (if any)

ELMA.COMPROFILESMODULE PROFILESThe VPX Modules and Slots across the backplanes have been given definitions so that similar Moduleswill work within certain Slot configurations. The backplane Slot Profile table describes the height, typeof slot (centralized, distributed or hybrid), the pitch, RTM connector, the corresponding payload andswitch cards that plug in, and the control and dataplane data rates.Profile NameData Plane 4 FPDP01DP02DP03Control Plane 2 TPsDP04CPtp01CPtp02MOD6-PAY-4F2T-12.2.2-1SRIO 1.3 at 3.125 Gbaud per Section 5.2.11000BASE-T per Section 5.1.3MOD6-PAY-4F2T-12.2.2-2PCIe Gen 1 per Section 5.3.3.11000BASE-T per Section 5.1.3MOD6-PAY-4F2T-12.2.2-3PCIe Gen 2 per Section 5.3.3.21000BASE-T per Section 5.1.3MOD6-PAY-4F2T-12.2.2-410GBASE-BX4 per Section 5.1.41000BASE-T per Section 5.1.3MOD6-PAY-4F2T-12.2.2-510GBASE-KX4 per Section 5.1.51000BASE-T per Section 5.1.3MOD6-PAY-4F2T-12.2.2-6SRIO 2.0 at 5.0 Gbaud per Section 5.2.21000BASE-T per Section 5.1.3MOD6-PAY-4F2T-12.2.2-7SRIO 2.0 at 6.25 Gbaud per Section 5.2.31000BASE-T per Section 5.1.3MOD6-PAY-4F2T-12.2.2-8SRIO 2.1 at 5.0 Gbaud per Section 5.2.41000BASE-T per Section 5.1.3MOD6-PAY-4F2T-12.2.2-9SRIO 2.1 at 6.25 Gbaud per Section 5.2.51000BASE-T per Section 5.1.3MOD6-PAY-4F2T-12.2.2-1040GBASE-KR4 per Section 5.1.81000BASE-T per Section 5.1.3CHALLENGING ENVIRONMENTSVPX systems are often deployed in harsh environmentsacross a range of defense and industrial applicationswhere excessive shock, vibration and high ambienttemperatures are common.VPX BACKPLANES5

ELMA.COMTOPOLOGIES AND DATA RATESTOPOLOGIESThe backplane configuration examples show the connectivity across the backplane for various planes. This includes the routing topologyacross the data plane and the connections across the expansion, control, management and utility planes. They also provide an illustrationof the slot types, whether payload, switch or legacy bus slots.Slot numbersare logicalphysical slotnumbers maybe differentPayloadslotsSwitch/ PayloadManagement slotsExpansionPlane(DFP)Data Plane(FP)FPTPControl Plane(UTP)UTPManagementPlane (IPMB)Utility PlaneIncludes PowerDATA RATESOpenVPX defines the data rates of each Plane (Control, Data and Expansion) on the Backplane. They begin at 1.25 Gbaud/link andcurrently exceed 6.25 Gbaud/link.Note: Gbaud refers to the useful data transmitted per second. Gbps is usually larger and includes additional signals such as parity bits and packet headers.Profile Name6MechanicalSlot Profiles and SectionGbaud RatePitch (in)RTM ConnPayloadPayload or PeripheralData Plane ChannelBKP3-CEN03-15.2.9-11.0VITA EN03-15.2.9-21.0VITA EN03-15.2.9-31.0VITA CEN03-15.2.9-41.0VITA 46.10SLT3-PAY-2F-14.2.7SLT3-PER-1F-14.3.28.0VPX BACKPLANES

ELMA.COMSIGNALING AND DATA RATESUTILITY SIGNALSJ0/P0 Pin/SignalDescriptionVs1High Voltage Power Input 1 Voltage specified in VITA 65. Capability per VITA 46.0 Table 4-5Vs2High Voltage Power Input 2 Voltage specified differently for 3U or 6U in VITA 65. Capability per VITA 46.0 Table 4-5Vs3Low Voltage Power Input 3 Voltage specified in VITA 65. Capability per VITA 46.0 Table 4-5GA[4:0]*, GAP*Geographical Address Inputs 0-4, Parity. Grounded in each slot per VITA 46.0 Table 7-1.SM[3:0]System Management connections bussed per Phillips Semiconductor I2C-Bus Specification, Version 2.1, January 2000AUX CLK /-Optional auxiliary reference clock (see ANSI/VITA 65) matched better than 8.5 pS and differentially terminated to 130 Ohms 10%.3.3V AUX3.3V Auxiliary power, System Management, 1.0 A per slot. /- 12V AUXAuxiliary Power Supplies, 1.0 A per slot.SYSRESET*System Reset, bussed to all slots & terminated w 5% 220-ohm pull-up resistors to 3.3V AUX & 1.8K-ohm pull-down to GND or equiv.REF CLK /-Reference Clock 25 MHz matched better than 8.5 pS and differentially terminated at each end with a resistor of 61.9 Ohms 1%.NVMRONon-Volatile Memory Read Only, bussed to all slots and pulled to 3.3V AUX through 5% 220 ohm resistorTCK, TMS, TRST*, TDI, TDOJTAG Signals, not bussed or terminated on the backplane.No PadThe construction of the connector wafer is such that there is no circuit pad in this locationJJ1/P1 Pin/SignalDescriptionGDiscrete1Optional single ended general purpose I/O signal, bussed to each slot.P1-VBATBattery Voltage, Bussed, 3V /- 15% source on the backplane.SYS CON*When grounded the backplane the SYS CON mode is set. Implemented in by a jumper at any slot to be so designated.MaskableReset*Optional local reset input to Plug-In Module in addition to global SYSRESET*. Implemented as “opt-in” via jumper at each slot.Table 3.7-2 Utility Plane Signals on J0Row i1GDiscrete123GNDP1-VBATRowh i Rowg h RowRowRowRowfgRowRow efRowRowdeRowc d Rowb c Rowa bRowRowRowRow a1Vs1Vs1Vs1Vs1No Pad*Vs2Vs2Vs2Vs22Vs1Vs1Vs1Vs1No Pad*Vs2Vs2Vs2Vs23Vs3Vs3Vs3Vs3No Pad*Vs3Vs3Vs3Vs34GND4GNDSM2SM3GND-12V AuxGNDSYSRESET*NVMROGND5SYS CON*5GNDGAP*GA4*GND3.3V AuxGNDSM0SM1GND6GND6GNDGA3*GA2*GND 12V REFCLK-REFCLK GNDGNDAUXCLK-AUX CLK GNDGND7Reserved89GND1011GND141516 UD pins in Row i can be assigned by Slot Profiles in Sections 10 and 14.UD12138UDGNDUDGNDMaskableReset*The pairs on Rows a thru h are assigned by Slot Profiles in Sections 10 and 14.GNDTable 3.7-4 Utility Plane Signals on J1VPX BACKPLANES7

ELMA.COMCONNECTORSBACKPLANE AND DAUGHTER CARD PINOUT CHARTThis chart shows the specification pinout of boththe backplane and daughter card for J2-J6. Notethe differences between the plug-in module and thebackplane (even and odd pins) for Row E and RowB. Although the number of rows is different, theconnector arrangement allows single-ended signalsin these areas. The backplane and daugther cardconnectors mate without issue.VPX CONNECTORRow GRow FRow EEvenOddRow DRow CRow BEvenOddRow ABackplaneJ2-J612345678Row iRow hRow gRow fRow eRow dRow cRow bRow 1-TDGNDLN3-TDGNDLN5-TDGNDLN7-TD-GND-J2LN1-TD GND-J2LN3-TD GND-J2LN5-TD GND-J2LN7-TD 0-TD GNDLN2-TD GNDLN4-TD GNDLN6-TD RD GND-J2LN3-RD GND-J2LN5-RD GND-J2LN7-RD 0-RD GNDLN2-RD GNDLN4-RD GNDLN6-RD GND9SEwafer9GNDGND-J2LN8-TD-LN8-TD GNDGND-J2LN8-RD-LN8-RD 10GNDLN9-TD-LN9-TD GND-J2GNDLN9-RD-LN9-RD GND-J2GND11SEwafer11GNDGND-J2LN10-TD-LN10-TD GNDGND-J2GND-J2GNDLN11-RD-LN11-RD LN12-TD-LN12-TD GNDGND-J212GND13SEwafer13LN11-TD- LN11-TD 14GND15SEwafer1516GNDGNDGND-J2LN13-TD- LN13-TD GNDGND-J2LN15-TD- LN15-TD GND-J2GNDLN13-RD-LN13-RD LN14-TD-LN14-TD GNDGND-J2GND-J2GNDLN15-RD-LN15-RD LN10-RD- LN10-RD GND-J2GNDLN12-RD- LN12-RD GND-J2GNDLN14-RD- LN14-RD GND-J2GNDWith the exception of J0 rows 1-6, OpenVPX daughter card connectors are constructed of alternating even and odd wafer elements. As a result of this design, the odd wafer rows have a SEpin in daughter card column “g” that corresponds to backplane wafer column “i”.Elma can provide backplanes with either TE MultiGig or EPT Velox connectors in accordance with ANSI-VITA 46. The EPT Velox is Standard on Elma VPX development backplanes.Backplanes can also be assembled with backplane connectors in accordance with ANSI VITA60 or 63 connectors or a combination of slots fitted with VITA 46, 60 or 63 connectors as theyare all footprint compatible, though not intermateable.CHARACTERISTICSOperating Voltage:50 Volts AC peak or DCCurrent:1 amp at 30 C (single circuit, free air)Temperature:-55 C to 105 CInsulation resistance:1000 megohms minimumTemperature rise vs. current:30 C maximum temperature at 1 amp load,EvenRoOdwdRowODD AND EVEN WAFER DESIGNVITA 46 Wafer - Even Differential Pair8VPX BACKPLANESVITA 46 Wafer - Odd Differential Pair

ELMA.COMCONNECTORSIPMB CONNECTOR (SMT)Number of Positions:5Number of Rows:1Operating Temperature:85.0 C (max)Contact Material:Phosphor BronzeFlammability Rating:UL 94 V-0Gender:MaleCurrent Rating:1.3A at @ 30 C riseMfg Part Number:Molex PicoBlade(tm) 53398-0571KEYING GUIDEVPX alignment and module keying is accomplished by the use of pins on the backplane and sockets on the daughter card. The pins havea flat side that can be oriented in five different positions: 0, 45, 90, 270 or 315 degrees. In standard development backplanes, each slothas a unique key combination.The chart below gives the recommended keying arrangement for 3U or 6U backplanes. Additionally, the key receptacle on the daughtercard has electrical contacts so that the keying is part of the VPX safety ground system. The backplane key orientation can be changed bythe user, and a daughter card receptacle key can be a full circle without a flat, which allows a daughter card to be placed over backplane keys of any orientation. Double-ended backplane guide modules provide RTM keying and alignment.BackplaneSlot*Voltage KeyPosition 1KeyPosition 2KeyPosition 3Slot 1315270270Slot 2315315270Slot 33150270Slot 431545270Slot 531590270Slot 6315270315Slot 7315315315Slot 83150315Slot 931545315Slot 1031590315Slot 113152700Slot 123153150Slot 13315000Slot 1431545Slot 15315900Slot 1631527045Slot 1731531545Slot 18315045Slot 193154545Slot 203159045Slot 2131527090Slot 2231531590BackplaneFTM RTMFront Module1469491-C1469492-CFront Rear Double Key*1410956-C1469492-CKeying PinKeying GuideDouble-Ended Guide* Double ended for backplane. FTM and RTM use sameVPX BACKPLANES9

ELMA.COMPOWER & VOLTAGE ASSIGNMENTSVPX - AVAILABLE POWER & VOLTAGE ASSIGNMENTSThe chart below gives maximum power perVPX slot based upon VITA 46 and profilesdefined in VITA 65.Voltage Level3Uwatts/slotwatts/slot6Uper waferdue to connector limitsOnly 3V69N/A23 Amps†Only 5V11511523 Amps†Only 12V*27638423 Amps† (3U), 16 Amps‡ (6U)VS1, VS2, and VS324034812 Amps§Only 48v per VITA 46N/A76816 Amps‡ (VS1 and VS2)Note: † 1 power wafer used, ‡ 2 power wafers used, § 3 power wafers usedThe assignment of voltages on VS1, VS2 and VS3 is different for 3U and 6U cards. In addition, more voltage options are alowed forVS1 and VS2 in VITA 46 than are currently defined within VITA 65.SIGNAL ASSIGNMENTS FOR THE J0 CONNECTOR PER VITA 46.0 AND VITA 653U POWER ASSIGNMENTS FOR THE J0 CONNECTOR PER VITA 656U POWER ASSIGNMENTS FOR THE J0 CONNECTOR PER VITA 6510VPX BACKPLANES

VPX SIGNAL INTEGRITYELMA.COMVPX SIGNAL INTEGRITY CONSIDERATIONSWith VPX backplanes pushing the speed envelope, every featureof the design can influence signal integrity – every trace, layerseparation, turn bend, via, via transition, etc. Elma’s signalintegrity analysis and simulations look at the entire channel inorder to ensure optimal performance.Our simulation is very detailed, looking closely at each elementin the channel. We focus on each of the various structures andlaunches, along with lossy trace models, to model the completechannel as accurately as possible. By focusing on each structureindividually, we can optimize the return loss for each. Once thestructures are modeled, they are concatenated together alongwith the lossy trace models and connector models to create thecomplete channel. When there are four complete coupled channels modeled - 2 TX and 2 RX - we utilize a connector modelthat also has four pairs. Transmission lines are created in W-element tabular format using RLGC, a 2D Field Solver. The fittedattenuation, IL, ILD, RL and ICR will be compared to the channel requirements. We use symmetry and algebraically add noise componentsto account for the total noise in the system. This total noise includes the coupled noise generated in the connector via fields as well as theconnectors themselves.We generate S-parameter models and run the simulation in Ansoft HFSS. For instance, when dealing with a typically thick 30-layerN4000-13EPSI backplane design, we need to ensure compliance to the stringent 10 Gbps KR frequency domain requirements. For eachsimulation, four complete channels (2-TX and 2-RX) are modeled. These channels are coupled together in the connector via footprintsas well as the connector models to account for the total noise generated. We start by modeling the worst-case channel parameters. Thiswould include a channel being routed on the lowest backplane layer (L28) in the stack. We will use the largest multilane connector modelavailable. For PCIe Gen3 analysis, SEASIM is the preferred tool for channel performance. If problems are encountered, specific recommendations for resolving those problems are recommended and verified via additional simulation.QUALITY BEGINS & ENDS WITH THE CUSTOMERThis is reflected throughout Elma. Our qualityprocedures meet ISO 9001 & AS9100C standards,ensuring that we meet the most rigorous requirements.VPX BACKPLANES11

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The VITA Standards Organization (VSO) is an ANSI-accredited group that provides members with a means to work together to define and develop key computer specifications such as the family of VPX standards, which include VITA 46.x, VITA 48.x, and VITA 65. Elma is a key contributor to the Work-ing Groups related to VPX. 46.0 VPX 46.1 Parallel VME .