Intel Quark SoC X1000DatasheetOctober 2013Document Number: 329676-001US

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OROTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONSOF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATINGTO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.Legal Lines and DisclaimersA "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death.SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL ANDITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST ALLCLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCTLIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITSSUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS.Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristicsof any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoeverfor conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a designwith this information.The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from publishedspecifications. Current characterized errata are available on request.Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-5484725, or go to: US 01Code Names are only for use by Intel to identify products, platforms, programs, services, etc. (“products”) in development by Intel that have not beenmade commercially available to the public, i.e., announced, launched or shipped. They are never to be used as “commercial” names for products. Also,they are not intended to function as trademarks.Intel and the Intel logo, are trademarks of Intel Corporation in the U.S. and other countries.*Other names and brands may be claimed as the property of others.Copyright 2013, Intel Corporation. All rights reserved.Intel Quark SoC X1000DS2October 2013Document Number: 329676-001US

—Intel Quark SoC X1000Contents1.0Introduction . 371.1About This Manual . 371.2Component Overview. 371.2.1 SoC CPU Core Features . 381.2.2 System Memory Controller Features . 391.2.3 Embedded SRAM Features . 391.2.4 Power Management Features . 391.2.5 Security Features . 391.2.6 PCI Express* Features . 391.2.7 Ethernet Features. 401.2.8 USB2 Host Controller Features . 401.2.9 USB2 Device Controller Features . 401.2.10 SD/SDIO/eMMC Controller Features . 401.2.11 I2C* Master Controller . 401.2.12 GPIO Features . 411.2.13 SPI Master Controller . 411.2.14 High Speed UART Controller with DMA . 411.2.15 Legacy Bridge . 411.2.16 Package . 411.3Component Identification . 412.0Physical Interfaces . 452.1Pin States Through Reset . 472.2System Memory Signals . 472.3PCI Express* 2.0 Signals. 482.4Ethernet Interface Signals . 492.5USB 2.0 Interface Signals. 492.6Integrated Clock Interface Signals . 502.7SDIO/SD/MMC Signals . 502.8High Speed UART Interface Signals. 512.9I2C* Interface Signals. 512.10 Legacy Serial Peripheral Interface (SPI) Signals. 522.11 Serial Peripheral Interface (SPI) . 522.12 Real Time Clock (RTC) Interface Signals . 532.13 Power Management Signals . 532.14 JTAG and Debug Interface Signals . 532.15 Legacy Interface Signals . 542.16 General Purpose I/O Interface Signals. 542.17 Power And Ground Pins . 552.18 Hardware Straps . 563.0Ballout and Package Information. 594.0Electrical Characteristics . 694.1Absolute Maximum Ratings. 694.2Recommended Power Supply Ranges . 704.3Maximum Supply Current . 714.4Configurable IO Characteristics . 724.5RTC DC Characteristics . 724.6PCI Express* 2.0 DC/AC Characteristics . 734.7USB 2.0 DC/AC Characteristics. 75October 2013Document Number: 329676-001USIntel Quark SoC X1000DS3

Intel Quark SoC X1000—4.84.9General Interface Timing .784.8.1 Legacy SPI Interface Timing.784.8.2 SPI0/1 Interface Timing.784.8.3 SDIO Interface Timing.79Clock AC Timing .804.9.1 Reference Clock AC Characteristics.805.0Register Access Methods.835.1Fixed I/O Register Access .835.2Fixed Memory Mapped Register Access .835.3I/O Referenced Register Access .835.4Memory Referenced Register Access.845.5PCI Configuration Register Access .845.5.1 PCI Configuration Access - CAM: I/O Indexed Scheme .845.5.2 PCI Configuration Access - ECAM: Memory Mapped Scheme .855.6Message Bus Register Access .865.7Register Field Access Types.876.0Mapping Address Spaces.896.1Physical Address Space Mappings.896.1.1 Bridge Memory Map .896.1.1.1 MMIO .916.1.1.2 DOS DRAM .926.1.1.3 Additional Mappings.926.1.2 MMIO Map .936.2I/O Address Space .936.2.1 Host Bridge I/O Map .946.2.2 I/O Fabric I/O Map.946.2.2.1 Legacy Bridge Fixed I/O Address Ranges .946.2.2.2 Variable I/O Address Ranges.946.3PCI Configuration Space .956.4Message Bus Space.977.0Clocking .997.1Clocking Features .997.2Platform/System Clock Domains . 1008.0Power Management . 1038.1Power Management Features. 1038.2ACPI Supported States . 1038.2.1 S-State Definition . 1038.2.1.1 S0 - Full On . 1038.2.1.2 S3 - Suspend to RAM (Standby) . 1038.2.1.3 S4 - Suspend to Disk (Hibernate) . 1038.2.1.4 S5 - Soft Off . 1048.2.2 System States. 1048.2.3 Processor Idle States. 1058.2.4 Integrated Memory Controller States . 1058.2.5 PCIe* States . 1058.2.6 Interface State Combinations . 1068.3Processor Core Power Management . 1068.3.1 Low-Power Idle States. 1068.3.1.1 Clock Control and Low-Power States . 1068.3.2 Processor Core C-States Description. 1068.3.2.1 Core C0 State . 1068.3.2.2 Core C1 State . 1078.3.2.3 Core C2 State . 107Intel Quark SoC X1000DS4October 2013Document Number: 329676-001US

—Intel Quark SoC X10008.49.0Memory Controller Power Management. 1078.4.1 Disabling Unused System Memory Outputs . 1078.4.2 DRAM Power Management and Initialization . 1078.4.2.1 Initialization Role of CKE . 1078.4.2.2 Dynamic Self-Refresh . 1078.4.2.3 Dynamic Power Down Operation . 1088.4.2.4 Functional Clock Gating . 108Power Up and Reset Sequence. 1099.1Intel Quark SoC X1000 System States . 1099.1.1 System Sleeping States Control (S-States) . 1099.2Power Up and Down Sequences. 1099.2.1 Power Up, Wake and Reset Overview . 1099.2.2 RTC Power Well Transition: G5 to G3 State Transition . 1109.2.3 Power-Up Sequence without G2/G3: No Coin-Cell Battery . 1119.2.4 AC Power Applied: G3 to S4/S5 State Transition . 1129.2.5 Using PWR BTN: Transition from S4/S5 to S0 . 1129.2.6 Going to Sleep: Transitions from S0 to S3 or S4/S5 . 1169.2.7 Wake Events: Transition from S3 to S0 . 1169.2.8 System Reset Sequences. 1169.2.8.1 Cold Boot Sequence . 1179.2.8.2 Cold Reset Sequence. 1179.2.8.3 Warm Reset Sequence (Internal) . 1179.2.8.4 Externally Initiated Warm Reset Sequence . 1179.2.9 Handling Power Failures . 11710.0 Thermal Management . 11910.1 Overview . 11910.2 Thermal Sensor. 11911.0 Processor Core . 12112.0 Host Bridge . 12312.1 Embedded SRAM (eSRAM). 12312.1.1 Initialization . 12312.1.2 Configuration. 12312.1.2.1 4KB Page Mode . 12312.1.2.2 512KB Block Page Mode. 12412.1.3 Configuration Locking . 12512.1.4 ECC Protection . 12612.1.5 Flush to DRAM . 12612.2 Isolated Memory Regions (IMR). 12612.2.1 IMR Violation . 12712.2.2 IMR Locking. 12712.3 Remote Management Unit DMA . 12712.3.1 ECC Scrubbing . 12812.4 Register Map . 12812.5 PCI Configuration Registers . 12912.5.1 PCI Device ID and Vendor ID Fields (PCI DEVICE VENDOR)—Offset 0h. 12912.5.2 PCI Status and Command Fields (PCI STATUS COMMAND)—Offset 4h . 12912.5.3 PCI Class Code and Revision ID Fields (PCI CLASS REVISION)—Offset 8h. 13012.5.4 PCI Miscellaneous Fields (PCI MISC)—Offset Ch . 13012.5.5 PCI Subsystem ID and Subsystem Vendor ID Fields(PCI SUBSYSTEM)—Offset 2Ch . 13112.5.6 Message Bus Control Register (MCR) (SB PACKET REG)—Offset D0h. 13212.5.7 Message Data Register (MDR) (SB DATA REG)—Offset D4h . 132October 2013Document Number: 329676-001USIntel Quark SoC X1000DS5

Intel Quark SoC X1000—12.612.712.5.8 Message Control Register eXtension (MCRX) (SB ADDR EXTN REG)—OffsetD8h . 13212.5.9 Manufacturer ID (PCI MANUFACTURER)—Offset F8h . 133IO Mapped Register . 13412.6.1 ACPI Processor Block. 13412.6.1.1 Processor Control (P CNT)—Offset 0h . 13412.6.1.2 Level 2 Register (P LVL2)—Offset 4h . 13512.6.1.3 C6 Control Register (P C6C)—Offset Ch . 13512.6.2 SPI DMA Block . 13612.6.2.1 SPI DMA Count Register (SPI DMA CNT IOSF)—Offset 0h . 13612.6.2.2 SPI DMA Destination Register (SPI DMA DST IOSF)—Offset 4h . 13612.6.2.3 SPI DMA Source Register (SPI DMA SRC IOSF)—Offset 8h . 137Message Bus Register. 13812.7.1 Host Bridge Arbiter (Port 0x00) . 13812.7.1.1 Enhanced Configuration Space (AEC CTRL)—Offset 0h . 13812.7.1.2 STATUS—Offset 21h . 13812.7.1.3 Requester ID Match Control (ASUBCHAN CTRL)—Offset 50h . 13912.7.1.4 Requester ID Match Sub-Channel 1 (ASUBCHAN1 MATCH)—Offset51h . 14012.7.1.5 Requester ID Match Sub-Channel 2 (ASUBCHAN2 MATCH)—Offset52h . 14112.7.1.6 Requester ID Match Sub-Channel 3 (ASUBCHAN3 MATCH)—Offset53h . 14112.7.2 Host Bridge (Port 0x03) . 14212.7.2.1 Host Miscellaneous Controls 2 (HMISC2)—Offset 3h . 14312.7.2.2 Host System Management Mode Controls (HSMMCTL)—Offset 4h. 14412.7.2.3 Host Memory I/O Boundary (HMBOUND)—Offset 8h . 14512.7.2.4 Extended Configuration Space (HECREG)—Offset 9h . 14612.7.2.5 Host Bridge Write Flush Control (HWFLUSH)—Offset Ch . 14712.7.2.6 MTRR Capabilities (MTRR CAP)—Offset 40h . 14712.7.2.7 MTRR Default Type (MTRR DEF TYPE)—Offset 41h. 14812.7.2.8 MTRR Fixed 64KB Range 0x00000 (MTRR FIX64K 00000)—Offset42h . 14812.7.2.9 MTRR Fixed 64KB Range 0x40000 (MTRR FIX64K 40000)—Offset43h . 14912.7.2.10MTRR Fixed 16KB Range 0x80000 (MTRR FIX16K 80000)—Offset44h . 14912.7.2.11MTRR Fixed 16KB Range 0x90000 (MTRR FIX16K 90000)—Offset45h . 15012.7.2.12MTRR Fixed 16KB Range 0xA0000 (MTRR FIX16K A0000)—Offset46h . 15112.7.2.13MTRR Fixed 16KB Range 0xB0000 (MTRR FIX16K B0000)—Offset47h . 15112.7.2.14MTRR Fixed 4KB Range 0xC0000 (MTRR FIX4K C0000)—Offset48h . 15212.7.2.15MTRR Fixed 4KB Range 0xC4000 (MTRR FIX4K C4000)—Offset49h . 15212.7.2.16MTRR Fixed 4KB Range 0xC8000 (MTRR FIX4K C8000)—Offset4Ah . 15312.7.2.17MTRR Fixed 4KB Range 0xCC000 (MTRR FIX4K CC000)—Offset4Bh . 15312.7.2.18MTRR Fixed 4KB Range 0xD0000 (MTRR FIX4K D0000)—Offset4Ch . 15412.7.2.19MTRR Fixed 4KB Range 0xD40000 (MTRR FIX4K D4000)—Offset4Dh. 15512.7.2.20MTRR Fixed 4KB Range 0xD8000 (MTRR FIX4K D8000)—Offset4Eh . 15512.7.2.21MTRR Fixed 4KB Range 0xDC000 (MTRR FIX4K DC000)—Offset4Fh . 156Intel Quark SoC X1000DS6October 2013Document Number: 329676-001US

—Intel Quark SoC X100012.7.2.22MTRR Fixed 4KB Range 0xE0000 (MTRR FIX4K E0000)—Offset50h. 15612.7.2.23MTRR Fixed 4KB Range 0xE4000 (MTRR FIX4K E4000)—Offset51h. 15712.7.2.24MTRR Fixed 4KB Range 0xE8000 (MTRR FIX4K E8000)—Offset52h. 15712.7.2.25MTRR Fixed 4KB Range 0xEC000 (MTRR FIX4K EC000)—Offset53h. 15812.7.2.26MTRR Fixed 4KB Range 0xF0000 (MTRR FIX4K F0000)—Offset54h. 15812.7.2.27MTRR Fixed 4KB Range 0xF4000 (MTRR FIX4K F4000)—Offset55h. 15912.7.2.28MTRR Fixed 4KB Range 0xF8000 (MTRR FIX4K F8000)—Offset56h. 16012.7.2.29MTRR Fixed 4KB Range 0xFC000 (MTRR FIX4K FC000)—Offset57h. 16012.7.2.30System Management Range Physical Base(MTRR SMRR PHYSBASE)—Offset 58h . 16112.7.2.31System Management Range Physical Mask(MTRR SMRR PHYSMASK)—Offset 59h. 16112.7.2.32MTRR Variable Range Physical Base 0(MTRR VAR PHYSBASE0)—Offset 5Ah. 16212.7.2.33MTRR Variable Range Physical Mask 0 (MTRR VAR PHYSMASK0)—Offset 5Bh . 16212.7.2.34MTRR Variable Range Physical Base 1(MTRR VAR PHYSBASE1)—Offset 5Ch. 16312.7.2.35MTRR Variable Range Physical Mask 1 (MTRR VAR PHYSMASK1)—Offset 5Dh . 16412.7.2.36MTRR Variable Range Physical Base 2(MTRR VAR PHYSBASE2)—Offset 5Eh . 16412.7.2.37MTRR Variable Range Physical Mask 2 (MTRR VAR PHYSMASK2)—Offset 5Fh. 16512.7.2.38MTRR Variable Range Physical Base 3(MTRR VAR PHYSBASE3)—Offset 60h . 16512.7.2.39MTRR Variable Range Physical Mask 3 (MTRR VAR PHYSMASK3)—Offset 61h . 16612.7.2.40MTRR Variable Range Physical Base 4(MTRR VAR PHYSBASE4)—Offset 62h . 16612.7.2.41MTRR Variable Range Physical Mask 4 (MTRR VAR PHYSMASK4)—Offset 63h . 16712.7.2.42MTRR Variable Range Physical Base 5(MTRR VAR PHYSBASE5)—Offset 64h . 16812.7.2.43MTRR Variable Range Physical Mask 5 (MTRR VAR PHYSMASK5)—Offset 65h . 16812.7.2.44MTRR Variable Range Physical Base 6(MTRR VAR PHYSBASE6)—Offset 66h . 16912.7.2.45MTRR Variable Range Physical Mask 6 (MTRR VAR PHYSMASK6)—Offset 67h . 16912.7.2.46MTRR Variable Range Physical Base 7(MTRR VAR PHYSBASE7)—Offset 68h . 17012.7.2.47MTRR Variable Range Physical Mask 7 (MTRR VAR PHYSMASK7)—Offset 69h . 17012.7.3 Remote Management Unit (Port 0x04) . 17112.7.3.1 ECC Scrubber Configuration Register (P CFG 50)—Offset 50h . 17112.7.3.2 SPI DMA Count Register (P CFG 60)—Offset 60h. 17212.7.3.3 SPI DMA Destination Register (P CFG 61)—Offset 61h . 17312.7.3.4 SPI DMA Source Register (P CFG 62)—Offset 62h . 17312.7.3.5 Processor Register Block (P BLK) Base Address(P CFG 70)—Offset 70h . 17412.7.3.6 Control Register (P CFG 71)—Offset 71h. 174October 2013Document Number: 329676-001USIntel Quark SoC X1000DS7

Intel Quark SoC X1000— Watchdog Control Register (P CFG 74)—Offset 74h . 17512.7.3.8 ECC Scrubber Start Address Register (P CFG 76)—Offset 76h . 17612.7.3.9 ECC Scrubber End Address Register (P CFG 77)—Offset 77h . 17612.7.3.10ECC Scrubber Next Address Register (P CFG 7C)—Offset 7Ch . 17712.7.3.11Thermal Sensor Mode Register (P CFG B0)—Offset B0h. 17812.7.3.12Thermal Sensor Temperature Register (P CFG B1)—Offset B1h . 17812.7.3.13Thermal Sensor Programmable Trip Point Register(P CFG B2)—Offset B2h . 17912.7.4 Memory Manager (Port 0x05) . 18012.7.4.1 Control (BCTRL)—Offset 1h . 18112.7.4.2 Write Flush Policy (BWFLUSH)—Offset 2h .

Intel Quark SoC X1000 DS October 2013 2 Document Number: 329676-001US Legal Lines and DisclaimersINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH IN TEL PRODUCTS.